LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 112

Manufacturer Part Number

KIT STUDENT LEARNING S12 DG128

Manufacturer

Freescale Semiconductor

Architecture

Code Gen Tools Included

Code Warrior

Silicon Manufacturer

Core Architecture

Core Sub-architecture

Silicon Core Number

Silicon Family Name

Kit Contents

HCS12 DG128 Learning Kit

Rohs Compliant

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

1. Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data source

Chapter 2 Port Integration Module (S12XEPIMV1)

Address 0x0000 (PRR)

Address 0x0001 (PRR)

is depending on the data direction value.

Write: Anytime. In emulation modes, write operations will also be directed to the external bus.

is depending on the data direction value.

Write: Anytime. In emulation modes, write operations will also be directed to the external bus.

Port A general purpose input/output data—Data Register

Port A pins 7 through 0 are associated with address outputs ADDR[15:8] respectively in expanded modes. In

emulation modes the address is multiplexed with IVD[15:8].

When not used with the alternative function, these pins can be used as general purpose I/O.

If the associated data direction bits of these pins are set to 1, a read returns the value of the port register, otherwise

the buffered pin input state is read.

Port A Data Register (PORTA)

Port B Data Register (PORTB)

Table 2-4. PORTA Register Field Descriptions

MC9S12XE-Family Reference Manual , Rev. 1.23

Figure 2-1. Port A Data Register (PORTA)

Figure 2-2. Port B Data Register (PORTB)

Access: User read/write

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