LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 1264
LFEBS12UB
Manufacturer Part Number
LFEBS12UB
Description
KIT STUDENT LEARNING S12 DG128
Manufacturer
Freescale Semiconductor
Specifications of LFEBS12UB
Architecture
8/16-bit
Code Gen Tools Included
Code Warrior
Silicon Manufacturer
Freescale
Core Architecture
S12
Core Sub-architecture
S12
Silicon Core Number
MC9S12
Silicon Family Name
S12D
Kit Contents
HCS12 DG128 Learning Kit
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Appendix C PCB Layout Guidelines
Appendix C
PCB Layout Guidelines
The PCB must be carefully laid out to ensure proper operation of the voltage regulator as well as of the
MCU itself. The following rules must be observed:
Example layouts are illustrated on the following pages.
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Every supply pair must be decoupled by a ceramic capacitor connected as near as possible to the
corresponding pins .
Central point of the ground star should be the VSS3 pin.
Use low ohmic low inductance connections between VSS1, VSS2 and VSS3.
VSSPLL must be directly connected to VSS3.
Keep traces of VSSPLL, EXTAL, and XTAL as short as possible and occupied board area for C7,
C8, and Q1 as small as possible.
Do not place other signals or supplies underneath area occupied by C7, C8, and Q1 and the
connection area to the MCU.
Central power input should be fed in at the VDDA/VSSA pins.
MC9S12XE-Family Reference Manual , Rev. 1.23
Freescale Semiconductor
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