LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 350

• Manufacturer Part Number: LFEBS12UB
• Description: KIT STUDENT LEARNING S12 DG128
• Manufacturer: Freescale Semiconductor

Specifications of LFEBS12UB

• Architecture: 8/16-bit
• Code Gen Tools Included: Code Warrior
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12D
• Kit Contents: HCS12 DG128 Learning Kit
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 9 Security (S12XE9SECV2)
9.1.2
Table 9-2
9.1.3
Once the user has programmed the Flash and EEPROM, the chip can be secured by programming the
security bits located in the options/security byte in the Flash memory array. These non-volatile bits will
keep the device secured through reset and power-down.
The options/security byte is located at address 0xFF0F (= global address 0x7F_FF0F) in the Flash memory
array. This byte can be erased and programmed like any other Flash location. Two bits of this byte are used
for security (SEC[1:0]). On devices which have a memory page window, the Flash options/security byte
is also available at address 0xBF0F by selecting page 0x3F with the PPAGE register. The contents of this
byte are copied into the Flash security register (FSEC) during a reset sequence.
The meaning of the bits KEYEN[1:0] is shown in
the MCU Using the Backdoor Key Access”
350
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
1. Availability of Flash arrays in the memory map depends on ROMCTL/EROMCTL pins and/or the state of the
2. Restricted NVM command set only. Please refer to the NVM wrapper block guides for detailed information.
3. BDM hardware commands restricted to peripheral registers only.
Internal accesses visible
EEPROM Array Access
ROMON/EROMON bits in the MMCCTL1 register. Please refer to the S12X_MMC block guide for detailed
information.
External Bus Interface
Internal status visible
Flash Array Access
DBG Module Trace
XGATE Debugging
NVM Commands
0xFF0F
gives an overview over availability of security relevant features in unsecure and secure modes.
on external bus
multiplexed on
external bus
Modes of Operation
Securing the Microcontroller
BDM
Table 9-2. Feature Availability in Unsecure and Secure Modes on S12XE
KEYEN1
7
KEYEN0
✔
NS
—
—
—
✔
✔
✔
✔
✔
(2)
MC9S12XE-Family Reference Manual , Rev. 1.23
6
Figure 9-1. Flash Options/Security Byte
SS
—
—
—
✔
✔
✔
✔
✔
✔
Unsecure Mode
NV5
✔
5
NX
✔
—
—
✔
✔
✔
✔
✔
(1)
2
for more information.
ES
✔
✔
—
✔
✔
✔
✔
✔
✔
1
2
Table
NV4
4
EX
✔
✔
—
✔
✔
✔
✔
✔
✔
1
2
9-3. Please refer to
NV3
ST
✔
—
✔
✔
✔
✔
✔
✔
✔
3
1
NS
✔
—
—
—
—
—
—
✔
✔
2
NV2
2
✔
SS
✔
—
—
—
—
—
✔
✔
(3)
2
Section 9.1.5.1, “Unsecuring
Secure Mode
NX
✔
—
—
—
—
—
—
—
✔
SEC1
2
1
Freescale Semiconductor
ES
✔
—
—
—
—
—
—
✔
✔
2
SEC0
EX
✔
—
—
—
—
—
—
✔
✔
0
2
✔
ST
—
—
—
—
—
—
✔
✔
2