LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 750

Manufacturer Part Number

KIT STUDENT LEARNING S12 DG128

Manufacturer

Freescale Semiconductor

Architecture

Code Gen Tools Included

Code Warrior

Silicon Manufacturer

Core Architecture

Core Sub-architecture

Silicon Core Number

Silicon Family Name

Kit Contents

HCS12 DG128 Learning Kit

Rohs Compliant

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Chapter 20 Serial Communication Interface (S12SCIV5)

The SCI receiver can accommodate either 8-bit or 9-bit data characters. The state of the M bit in SCI

control register 1 (SCICR1) determines the length of data characters. When receiving 9-bit data, bit R8 in

SCI data register high (SCIDRH) is the ninth bit (bit 8).

During an SCI reception, the receive shift register shifts a frame in from the RXD pin. The SCI data register

is the read-only buffer between the internal data bus and the receive shift register.

After a complete frame shifts into the receive shift register, the data portion of the frame transfers to the

SCI data register. The receive data register full ﬂag, RDRF, in SCI status register 1 (SCISR1) becomes set,

From TXD Pin

or Transmitter

Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers

indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010

Receiver Character Length

Character Reception

Baud Divider

MC9S12XE-Family Reference Manual , Rev. 1.23

Figure 20-20. SCI Receiver Block Diagram

Detect Logic

Detect Logic

Internal Bus

11-Bit Receive Shift Register

SCI Data Register

Freescale Semiconductor

RX Active Edge IRQ