LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 579

• Manufacturer Part Number: LFEBS12UB
• Description: KIT STUDENT LEARNING S12 DG128
• Manufacturer: Freescale Semiconductor

Specifications of LFEBS12UB

• Architecture: 8/16-bit
• Code Gen Tools Included: Code Warrior
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12D
• Kit Contents: HCS12 DG128 Learning Kit
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.4.2
The reset state of each individual bit is listed within the register description section
“Memory Map and Register
14.4.3
This section describes interrupts originated by the ECT block. The MCU must service the interrupt
requests.
The ECT only originates interrupt requests. The following is a description of how the module makes a
request and how the MCU should acknowledge that request. The interrupt vector offset and interrupt
number are chip dependent.
14.4.3.1
This active high output will be asserted by the module to request a timer channel 7–0 interrupt to be
serviced by the system controller.
14.4.3.2
This active high output will be asserted by the module to request a modulus counter underflow interrupt to
be serviced by the system controller.
14.4.3.3
This active high output will be asserted by the module to request a timer pulse accumulator B overflow
interrupt to be serviced by the system controller.
14.4.3.4
This active high output will be asserted by the module to request a timer pulse accumulator A input
interrupt to be serviced by the system controller.
Freescale Semiconductor
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indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Table 14-39
Timer channel 7–0
Modulus counter underflow
Pulse accumulator B overflow
Pulse accumulator A input
Pulse accumulator A overflow
Timer overflow
Reset
Interrupts
Channel [7:0] Interrupt
Modulus Counter Interrupt
Pulse Accumulator B Overflow Interrupt
Pulse Accumulator A Input Interrupt
Interrupt Source
lists the interrupts generated by the ECT to communicate with the MCU.
Definition”) which details the registers and their bit-fields.
MC9S12XE-Family Reference Manual Rev. 1.23
Table 14-39. ECT Interrupts
Active high timer channel interrupts 7–0
Active high modulus counter interrupt
Active high pulse accumulator B interrupt
Active high pulse accumulator A input interrupt
Pulse accumulator overflow interrupt
Timer 0verflow interrupt
Description
Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
(Section 14.3,
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