LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 803

Manufacturer Part Number

KIT STUDENT LEARNING S12 DG128

Manufacturer

Freescale Semiconductor

Architecture

Code Gen Tools Included

Code Warrior

Silicon Manufacturer

Core Architecture

Core Sub-architecture

Silicon Core Number

Silicon Family Name

Kit Contents

HCS12 DG128 Learning Kit

Rohs Compliant

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Read: Anytime

Write: Anytime.

22.3.2.10 Timer Interrupt Enable Register (TIE)

Read: Anytime

Write: Anytime.

Freescale Semiconductor

Module Base + 0x000C

Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers

indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010

Input Capture Edge Control — These eight pairs of control bits conﬁgure the input capture edge detector

Input Capture/Output Compare “x” Interrupt Enable — The bits in TIE correspond bit-for-bit with the bits in

the TFLG1 status register. If cleared, the corresponding ﬂag is disabled from causing a hardware interrupt. If set,

the corresponding ﬂag is enabled to cause a interrupt.

Figure 22-18. Timer Interrupt Enable Register (TIE)

Table 22-12. Edge Detector Circuit Conﬁguration

Table 22-11. TCTL3/TCTL4 Field Descriptions

MC9S12XE-Family Reference Manual Rev. 1.23

Table 22-13. TIE Field Descriptions

Capture on any edge (rising or falling)

Capture on falling edges only

Capture on rising edges only

Capture disabled

Conﬁguration

Chapter 22 Timer Module (TIM16B8CV2) Block Description