LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 378

Manufacturer Part Number

KIT STUDENT LEARNING S12 DG128

Manufacturer

Freescale Semiconductor

Architecture

Code Gen Tools Included

Code Warrior

Silicon Manufacturer

Core Architecture

Core Sub-architecture

Silicon Core Number

Silicon Family Name

Kit Contents

HCS12 DG128 Learning Kit

Rohs Compliant

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Chapter 10 XGATE (S12XGATEV3)

The XGATE module offers a set of eight hardware semaphores. These semaphores provide a mechanism

to protect system resources that are shared between two concurrent threads of program execution; one

thread running on the S12X_CPU and one running on the XGATE RISC core.

Each semaphore can only be in one of the three states: “Unlocked”, “Locked by S12X_CPU”, and “Locked

by XGATE”. The S12X_CPU can check and change a semaphore’s state through the XGATE semaphore

this through its SSEM and CSEM instructions.

IFigure 10-24

Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers

indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010

illustrates the valid state transitions.

Channel $09 Initial Program Counter

Channel $09 Initial Data Pointer

Channel $0A Initial Program Counter

Channel $0A Initial Data Pointer

Channel $0B Initial Program Counter

Channel $0B Initial Data Pointer

Channel $0C Initial Program Counter

Channel $0C Initial Data Pointer

Channel $78 Initial Program Counter

Channel $78 Initial Data Pointer

Section 10.3.1.10, “XGATE Semaphore Register

MC9S12XE-Family Reference Manual , Rev. 1.23

Figure 10-23. XGATE Vector Block

(XGSEM)”). The RISC core does

Freescale Semiconductor