LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 499

• Manufacturer Part Number: LFEBS12UB
• Description: KIT STUDENT LEARNING S12 DG128
• Manufacturer: Freescale Semiconductor

Specifications of LFEBS12UB

• Architecture: 8/16-bit
• Code Gen Tools Included: Code Warrior
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12D
• Kit Contents: HCS12 DG128 Learning Kit
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

S12XECRG performs a quality check on the incoming clock signal. As soon as clock quality check
indicates a valid Oscillator Clock signal the reset sequence starts using the Oscillator clock. If after 50
check windows the clock quality check indicated a non-valid Oscillator Clock the reset sequence starts
using Self-Clock Mode.
Figure 11-22
and when the RESET pin is held low.
11.6
The interrupts/reset vectors requested by the S12XECRG are listed in
specification for related vector addresses and priorities.
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Interrupts
and
Figure 11-23
Internal RESET
Internal RESET
RESET
Internal POR
RESET
Internal POR
Figure 11-22. RESET Pin Tied to V
Interrupt Source
Real time interrupt
LOCK interrupt
SCM interrupt
Figure 11-23. RESET Pin Held Low Externally
show the power-up sequence for cases when the RESET pin is tied to V
MC9S12XE-Family Reference Manual Rev. 1.23
Table 11-18. S12XECRG Interrupt Vectors
Mask
Clock Quality Check
(no Self-Clock Mode)
Clock Quality Check
(no Self Clock Mode)
CCR
I bit
I bit
I bit
128 SYSCLK
) (
) (
) (
128 SYSCLK
) (
) (
) (
Chapter 11 S12XE Clocks and Reset Generator (S12XECRGV1)
64 SYSCLK
64 SYSCLK
DD
(by a Pull-up Resistor)
CRGINT (LOCKIE)
CRGINT (SCMIE)
CRGINT (RTIE)
Local Enable
Table
11-18. Refer to MCU
DD
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