LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 567

KIT STUDENT LEARNING S12 DG128

LFEBS12UB

Manufacturer Part Number
LFEBS12UB
Description
KIT STUDENT LEARNING S12 DG128
Manufacturer
Freescale Semiconductor
Datasheets

Specifications of LFEBS12UB

Architecture
8/16-bit
Code Gen Tools Included
Code Warrior
Silicon Manufacturer
Freescale
Core Architecture
S12
Core Sub-architecture
S12
Silicon Core Number
MC9S12
Silicon Family Name
S12D
Kit Contents
HCS12 DG128 Learning Kit
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
14.3.2.32 Timer Input Capture Holding Registers 0–3 (TCxH)
Freescale Semiconductor
Module Base + 0x0038
Module Base + 0x0039
Module Base + 0x003A
Module Base + 0x003B
Module Base + 0x003C
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
Reset
Reset
Reset
Reset
Reset
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
W
W
W
W
W
R
R
R
R
R
TC15
TC15
TC15
TC7
TC7
15
15
15
0
0
0
0
0
7
7
Figure 14-59. Timer Input Capture Holding Register 0 High (TC0H)
Figure 14-61. Timer Input Capture Holding Register 1 High (TC1H)
Figure 14-63. Timer Input Capture Holding Register 2 High (TC2H)
Figure 14-60. Timer Input Capture Holding Register 0 Low (TC0H)
Figure 14-62. Timer Input Capture Holding Register 1 Low (TC1H)
= Unimplemented or Reserved
= Unimplemented or Reserved
= Unimplemented or Reserved
= Unimplemented or Reserved
= Unimplemented or Reserved
TC14
TC14
TC14
TC6
TC6
14
14
14
0
0
0
0
0
6
6
MC9S12XE-Family Reference Manual Rev. 1.23
TC13
TC13
TC13
TC5
TC5
13
13
13
0
5
0
0
5
0
0
TC12
TC12
TC12
TC4
TC4
12
12
12
0
0
0
0
0
4
4
TC11
TC11
TC11
TC3
TC3
11
11
11
0
0
0
0
0
3
3
Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
TC10
TC10
TC10
TC2
TC2
10
10
10
0
2
0
0
2
0
0
TC9
TC1
TC9
TC1
TC9
0
0
0
0
0
9
1
9
1
9
TC8
TC0
TC8
TC0
TC8
0
0
0
0
0
8
0
8
0
8
567

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