LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 249

• Manufacturer Part Number: LFEBS12UB
• Description: KIT STUDENT LEARNING S12 DG128
• Manufacturer: Freescale Semiconductor

Specifications of LFEBS12UB

• Architecture: 8/16-bit
• Code Gen Tools Included: Code Warrior
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12D
• Kit Contents: HCS12 DG128 Learning Kit
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.3
This section provides a detailed description of all registers accessible in the XEBI.
5.3.1
The registers associated with the XEBI block are shown in
5.3.2
The following sub-sections provide a detailed description of each register and the individual register bits.
All control bits can be written anytime, but this may have no effect on the related function in certain
operating modes. This allows specific configurations to be set up before changing into the target operating
mode.
5.3.2.1
Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other
modes, the data is read from this register.
Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
Freescale Semiconductor
Module Base +0x000E (PRR)
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
EBICTL0
EBICTL1
Register
Reset
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Name
0x0E
0x0F
W
R
Memory Map and Register Definition
ITHRS
Module Memory Map
Register Descriptions
External Bus Interface Control Register 0 (EBICTL0)
0
7
W
W
R
R
Depending on the operating mode an available function may be enabled,
disabled or depend on the control register bit. Reading the register bits will
reflect the status of related function only if the current operating mode
allows user control. Please refer the individual bit descriptions.
ITHRS
Bit 7
= Unimplemented or Reserved
Figure 5-3. External Bus Interface Control Register 0 (EBICTL0)
0
0
0
6
= Unimplemented or Reserved
EXSTR12
MC9S12XE-Family Reference Manual Rev. 1.23
6
0
Figure 5-2. XEBI Register Summary
HDBE
5
1
EXSTR11
HDBE
5
ASIZ4
NOTE
1
4
EXSTR10
ASIZ4
4
Figure
ASIZ3
1
3
ASIZ3
3
0
5-2.
Chapter 5 External Bus Interface (S12XEBIV4)
ASIZ2
EXSTR02
2
1
ASIZ2
2
EXSTR01
ASIZ1
ASIZ1
1
1
1
EXSTR00
ASIZ0
ASIZ0
Bit 0
1
0
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