LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 542

Manufacturer Part Number

KIT STUDENT LEARNING S12 DG128

Manufacturer

Freescale Semiconductor

Architecture

Code Gen Tools Included

Code Warrior

Silicon Manufacturer

Core Architecture

Core Sub-architecture

Silicon Core Number

Silicon Family Name

Kit Contents

HCS12 DG128 Learning Kit

Rohs Compliant

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Chapter 14 Enhanced Capture Timer (ECT16B8CV3)

Read or write: Anytime

All bits reset to zero.

Module Base + 0x0008

Module Base + 0x0009

Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers

indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010

OMx — Output Mode

OLx — Output Level

These eight pairs of control bits are encoded to specify the output action to be taken as a result of a successful

OCx compare. When either OMx or OLx is one, the pin associated with OCx becomes an output tied to OCx.

Timer Control Register 1/Timer Control Register 2 (TCTL1/TCTL2)

To enable output action by OMx and OLx bits on timer port, the

corresponding bit in OC7M should be cleared. The settings for these bits can

Figure 14-11. Timer Control Register 1 (TCTL1)

Figure 14-12. Timer Control Register 2 (TCTL2)

Table 14-9. TCTL1/TCTL2 Field Descriptions

Table 14-10. Compare Result Output Action

MC9S12XE-Family Reference Manual Rev. 1.23

No output compare

action on the timer output signal

Toggle OCx output line

Clear OCx output line to zero

Set OCx output line to one

Freescale Semiconductor