LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 635

Manufacturer Part Number

KIT STUDENT LEARNING S12 DG128

Manufacturer

Freescale Semiconductor

Architecture

Code Gen Tools Included

Code Warrior

Silicon Manufacturer

Core Architecture

Core Sub-architecture

Silicon Core Number

Silicon Family Name

Kit Contents

HCS12 DG128 Learning Kit

Rohs Compliant

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Reset: Undeﬁned because of RAM-based implementation

The identiﬁer registers for an extended format identiﬁer consist of a total of 32 bits: ID[28:0], SRR, IDE,

and RTR. The identiﬁer registers for a standard format identiﬁer consist of a total of 13 bits: ID[10:0],

RTR, and IDE.

Freescale Semiconductor

For transmit buffers, anytime when TXEx ﬂag is set (see

Flag Register

Section 16.3.2.11, “MSCAN Transmit Buffer Selection Register

For receive buffers, only when RXF ﬂag is set (see

For transmit buffers, anytime when TXEx ﬂag is set (see

Flag Register

Section 16.3.2.11, “MSCAN Transmit Buffer Selection Register

Unimplemented for receive buffers.

Figure 16-24. Receive/Transmit Message Buffer — Extended Identiﬁer Mapping (continued)

Identiﬁer Registers (IDR0–IDR3)

Figure 16-25. Receive/Transmit Message Buffer — Standard Identiﬁer Mapping

(CANRFLG)”).

(CANTFLG)”) and the corresponding transmit buffer is selected in CANTBSEL (see

= Unused, always read ‘x’

MC9S12XE-Family Reference Manual Rev. 1.23

Chapter 16 Freescale’s Scalable Controller Area Network (S12MSCANV3)

Section 16.3.2.5, “MSCAN Receiver Flag

Section 16.3.2.7, “MSCAN Transmitter

(CANTBSEL)”).