LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 540

• Manufacturer Part Number: LFEBS12UB
• Description: KIT STUDENT LEARNING S12 DG128
• Manufacturer: Freescale Semiconductor

Specifications of LFEBS12UB

• Architecture: 8/16-bit
• Code Gen Tools Included: Code Warrior
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12D
• Kit Contents: HCS12 DG128 Learning Kit
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
Read: Anytime
Write: Writable in special modes.
All bits reset to zero.
14.3.2.6
Read or write: Anytime except PRNT bit is write once
All bits reset to zero.
540
Module Base + 0x0005
Module Base + 0x0006
TCNT[15:0]
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
TSWAI
Reset
Reset
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Field
Field
TEN
15:0
7
6
W
W
R
R
TCNT7
Timer Counter Bits — The 16-bit main timer is an up counter. A read to this register will return the current value
of the counter.
Note: A separate read/write for high byte and low byte in test mode will give a different result than accessing
TEN
Timer Enable
0 Disables the main timer, including the counter. Can be used for reducing power consumption.
1 Allows the timer to function normally.
Note: If for any reason the timer is not active, there is no ÷64 clock for the pulse accumulator since the ÷64 is
Timer Module Stops While in Wait
0 Allows the timer module to continue running during wait.
1 Disables the timer counter, pulse accumulators and modulus down counter when the MCU is in wait mode.
Timer System Control Register 1 (TSCR1)
0
0
7
7
Timer interrupts cannot be used to get the MCU out of wait.
them as a word. The period of the first count after a write to the TCNT registers may be a different size
because the write is not synchronized with the prescaler clock.
generated by the timer prescaler.
= Unimplemented or Reserved
TCNT6
TSWAI
Figure 14-9. Timer System Control Register 1 (TSCR1)
0
0
6
6
Access to the counter register will take place in one clock cycle.
Figure 14-8. Timer Count Register Low (TCNT)
MC9S12XE-Family Reference Manual Rev. 1.23
Table 14-7. TSCR1 Field Descriptions
Table 14-6. TCNT Field Descriptions
TCNT5
TSFRZ
5
0
5
0
TCNT4
TFFCA
0
0
4
4
Description
Description
TCNT3
PRNT
0
0
3
3
TCNT2
2
0
2
0
0
Freescale Semiconductor
TCNT1
0
0
0
1
1
TCNT0
0
0
0
0
0