LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 80

• Manufacturer Part Number: LFEBS12UB
• Description: KIT STUDENT LEARNING S12 DG128
• Manufacturer: Freescale Semiconductor

Specifications of LFEBS12UB

• Architecture: 8/16-bit
• Code Gen Tools Included: Code Warrior
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12D
• Kit Contents: HCS12 DG128 Learning Kit
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 1 Device Overview MC9S12XE-Family
MPU is set, access to system resources is only allowed if enabled by a memory range descriptor as defined
in the Memory Protection Unit (MPU) description.
1.4.4.2
This state is intended for carrying out system tasks and is entered by setting the U bit of the condition codes
register while in Supervisor state. Restrictions apply for the execution of several CPU instructions in User
state and access to system resources is only allowed in if enabled by a memory range descriptor as defined
in the Memory Protection Unit (MPU) description.
1.5
The MCU security feature allows the protection of the on chip Flash and emulated EEPROM memory. For
a detailed description of the security features refer to the S12X9SEC description.
1.6
Consult the S12XCPU manual and the S12XINT description for information on exception processing.
1.6.1
Resets are explained in detail in the Clock Reset Generator (CRG) description.
1.6.2
Table 1-14
(S12XINT) provides an interrupt vector base register (IVBR) to relocate the vectors. Associated with each
I-bit maskable service request is a configuration register. It selects if the service request is enabled, the
service request priority level and whether the service request is handled either by the S12X CPU or by the
XGATE module.
80
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indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Vector Address
Security
Resets and Interrupts
lists all interrupt sources and vectors in the default order of priority. The interrupt module
Resets
Vectors
$FFFE
$FFFE
$FFFE
$FFFE
$FFFC
User State
$FFFA
Table 1-13. Reset Sources and Vector Locations
MC9S12XE-Family Reference Manual , Rev. 1.23
Low Voltage Reset (LVR)
Power-On Reset (POR)
Illegal Address Reset
COP watchdog reset
External pin RESET
Clock monitor reset
Reset Source
Mask
None
None
None
None
None
None
CCR
PLLCTL (CME, SCME)
COP rate select
Local Enable
None
None
None
None
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