LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 642

Manufacturer Part Number

KIT STUDENT LEARNING S12 DG128

Manufacturer

Freescale Semiconductor

Architecture

Code Gen Tools Included

Code Warrior

Silicon Manufacturer

Core Architecture

Core Sub-architecture

Silicon Core Number

Silicon Family Name

Kit Contents

HCS12 DG128 Learning Kit

Rohs Compliant

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Chapter 16 Freescale’s Scalable Controller Area Network (S12MSCANV3)

1. Read: Anytime when TXEx ﬂag is set (see

Module Base + 0x00XF

corresponding transmit buffer is selected in CANTBSEL (see

(CANTBSEL)”)

Write: Unimplemented

Figure 16-38. Time Stamp Register — Low Byte (TSRL)

MC9S12XE-Family Reference Manual , Rev. 1.23

Section 16.3.2.7, “MSCAN Transmitter Flag Register

Section 16.3.2.11, “MSCAN Transmit Buffer Selection Register

(CANTFLG)”) and the

Access: User read/write

Freescale Semiconductor