LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 447

KIT STUDENT LEARNING S12 DG128

LFEBS12UB

Manufacturer Part Number
LFEBS12UB
Description
KIT STUDENT LEARNING S12 DG128
Manufacturer
Freescale Semiconductor
Datasheets

Specifications of LFEBS12UB

Architecture
8/16-bit
Code Gen Tools Included
Code Warrior
Silicon Manufacturer
Freescale
Core Architecture
S12
Core Sub-architecture
S12
Silicon Core Number
MC9S12
Silicon Family Name
S12D
Kit Contents
HCS12 DG128 Learning Kit
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
ROR
Operation
n = RS or IMM4
Rotates the bits in register RD n positions to the right. The upper n bits of the register RD are filled with
the lower n bits. Two source forms are available. In the first form, the parameter n is contained in the
instruction code as an immediate operand. In the second form, the parameter is contained in the lower bits
of the source register RS[3:0]. All other bits in RS are ignored. If n is zero no shift will take place and the
register RD will be unaffected; however, the condition code flags will be updated.
CCR Effects
Code and CPU Cycles
Freescale Semiconductor
N:
Z:
V:
C:
ROR RD, #IMM4
ROR RD, RS
N
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Set if bit 15 of the result is set; cleared otherwise.
Set if the result is $0000; cleared otherwise.
0; cleared.
Not affected.
Z
V
0
Source Form
C
MC9S12XE-Family Reference Manual Rev. 1.23
Address
Mode
IMM4
DYA
Rotate Right
0
0
0
0
n bits
RD
0
0
0
0
1
1
Machine Code
RD
RD
RS
IMM4
Chapter 10 XGATE (S12XGATEV3)
1
1
0
1
1
ROR
1
1
1
1
Cycles
P
P
447

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