LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 1251

KIT STUDENT LEARNING S12 DG128

LFEBS12UB

Manufacturer Part Number
LFEBS12UB
Description
KIT STUDENT LEARNING S12 DG128
Manufacturer
Freescale Semiconductor
Datasheets

Specifications of LFEBS12UB

Architecture
8/16-bit
Code Gen Tools Included
Code Warrior
Silicon Manufacturer
Freescale
Core Architecture
S12
Core Sub-architecture
S12
Silicon Core Number
MC9S12
Silicon Family Name
S12D
Kit Contents
HCS12 DG128 Learning Kit
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Freescale Semiconductor
No.
-
-
-
UDS, LDS
Frequency of internal bus
Internal cycle time
Frequency of external bus
ADDRx
EWAIT
DATAx
CSx
WE
RE
Table A-31. Example 1b: Normal Expanded Mode Timing at 50MHz bus (EWAIT enabled)
Characteristic
Figure A-14. Example 1b: Normal Expanded Mode — Stretched Write Access
4
12
9
MC9S12XE-Family Reference Manual Rev. 1.23
Symbol
t
cyc
f
f
o
i
13
C
-
-
-
D.C.
D.C.
Min
20
1
2 stretch
cycles
V
ADDR1
(Write) DATA1
DD5
Max
50.0
16.7
10
5
= 5.0V
D.C.
D.C.
Min
20
3 stretch
cycles
Max
50.0
12.5
C
-
-
-
Appendix A Electrical Characteristics
D.C.
D.C.
Min
20
2 stretch
cycles
V
11
DD5
Max
25.0
8.33
= 3.3V
D.C.
D.C.
Min
20
3 stretch
cycles
ADDR2
Max
25.0
6.25
MHz
MHz
1251
Unit
ns

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