LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 679

• Manufacturer Part Number: LFEBS12UB
• Description: KIT STUDENT LEARNING S12 DG128
• Manufacturer: Freescale Semiconductor

Specifications of LFEBS12UB

• Architecture: 8/16-bit
• Code Gen Tools Included: Code Warrior
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12D
• Kit Contents: HCS12 DG128 Learning Kit
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 18
Periodic Interrupt Timer (S12PIT24B4CV2)
18.1
The period interrupt timer (PIT) is an array of 24-bit timers that can be used to trigger peripheral modules
or raise periodic interrupts. Refer to
18.1.1
18.1.2
The PIT includes these features:
18.1.3
Refer to the device overview for a detailed explanation of the chip modes.
Freescale Semiconductor
Revision
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
Number
V01.00
V01.01
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
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micro time bases
Four timers implemented as modulus down-counters with independent time-out periods.
Time-out periods selectable between 1 and 2
cycles with 1 <= m <= 256 and 1 <= n <= 65536.
Timers that can be enabled individually.
Four time-out interrupts.
Four time-out trigger output signals available to trigger peripheral modules.
Start of timer channels can be aligned to each other.
Introduction
Glossary
Features
Modes of Operation
CCR
SoC
28 Apr 2005
PIT
ISR
05 Jul 2005
Revision
Date
18.6/18-692
Sections
Affected
Periodic Interrupt Timer
Interrupt Service Routine
Condition Code Register
System on Chip
clock periods of the 16-bit timer modulus down-counters, which are generated by the 8-bit
modulus down-counters.
MC9S12XE-Family Reference Manual , Rev. 1.23
Figure 18-1
Table 18-1. Revision History
Acronyms and Abbreviations
- Initial Release
- Added application section.
- Removed table 1-1
for a simplified block diagram.
24
bus clock cycles. Time-out equals m*n bus clock
Description of Changes
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