LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 357

KIT STUDENT LEARNING S12 DG128

LFEBS12UB

Manufacturer Part Number
LFEBS12UB
Description
KIT STUDENT LEARNING S12 DG128
Manufacturer
Freescale Semiconductor
Datasheets

Specifications of LFEBS12UB

Architecture
8/16-bit
Code Gen Tools Included
Code Warrior
Silicon Manufacturer
Freescale
Core Architecture
S12
Core Sub-architecture
S12
Silicon Core Number
MC9S12
Silicon Family Name
S12D
Kit Contents
HCS12 DG128 Learning Kit
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
10.1.3
There are four run modes on S12XE devices.
10.1.4
Figure 10-1
Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Provides up to 108 XGATE channels, including 8 software triggered channels
Interruptible thread execution
Two register banks to support fast context switching between threads
Hardware semaphores which are shared between the S12X_CPU and the XGATE module
Able to trigger S12X_CPU interrupts upon completion of an XGATE transfer
Software error detection to catch erratic application code
Run mode, wait mode, stop mode
The XGATE is able to operate in all of these three system modes. Clock activity will be
automatically stopped when the XGATE module is idle.
Freeze mode (BDM active)
In freeze mode all clocks of the XGATE module may be stopped, depending on the module
configuration (see
Modes of Operation
Block Diagram
shows a block diagram of the XGATE.
Peripherals
Peripheral Interrupts
Software
Interrupt
Triggers
SWE
Section 10.3.1.1, “XGATE Control Register
XGATE
Software Error Logic
Interrupt Flags
Software Triggers
MC9S12XE-Family Reference Manual Rev. 1.23
Semaphores
Figure 10-1. XGATE Block Diagram
S12X_INT
S12X_MMC
RISC Core
(XGMCTL)”).
S12X_DBG
Chapter 10 XGATE (S12XGATEV3)
357

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