LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 191

Manufacturer Part Number

KIT STUDENT LEARNING S12 DG128

Manufacturer

Freescale Semiconductor

Architecture

Code Gen Tools Included

Code Warrior

Silicon Manufacturer

Core Architecture

Core Sub-architecture

Silicon Core Number

Silicon Family Name

Kit Contents

HCS12 DG128 Learning Kit

Rohs Compliant

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Memory Mapping Control (S12XMMCV4)

This section describes the functionality of the module mapping control (MMC) sub-block of the S12X

platform. The block diagram of the MMC is shown in

The MMC module controls the multi-master priority accesses, the selection of internal resources and

external space. Internal buses, including internal memories and peripherals, are controlled in this module.

The local address space for each master is translated to a global memory space.

Freescale Semiconductor

Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers

indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010

Introduction

Revision Date

3.4.2.4/3-216

MC9S12XE-Family Reference Manual , Rev. 1.23

Table 3-1. Revision History

- Reorganization of MEMCTL0 register bits.

- Updated XGATE Memory Map

- Adding AUTOSAR Compliance concerning illegal CPU accesses

Description of Changes