LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 427

• Manufacturer Part Number: LFEBS12UB
• Description: KIT STUDENT LEARNING S12 DG128
• Manufacturer: Freescale Semiconductor

Specifications of LFEBS12UB

• Architecture: 8/16-bit
• Code Gen Tools Included: Code Warrior
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12D
• Kit Contents: HCS12 DG128 Learning Kit
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

CPC
Operation
RS1 – RS2 - C ⇒ NONE (translates to SBC R0, RS1, RS2)
Subtracts the carry bit and the content of register RS2 from the content of register RS1 using binary
subtraction and discards the result.
CCR Effects
Code and CPU Cycles
Freescale Semiconductor
N:
Z:
V:
C:
CPC RS1, RS2
N
∆
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Set if bit 15 of the result is set; cleared otherwise.
Set if the result is $0000; cleared otherwise.
Set if a two´s complement overflow resulted from the operation; cleared otherwise.
RS1[15] & RS2[15] & result[15] | RS1[15] & RS2[15] & result[15]
Set if there is a carry from the bit 15 of the result; cleared otherwise.
RS1[15] & RS2[15] | RS1[15] & result[15] | RS2[15] & result[15]
Z
∆
V
∆
Source Form
C
∆
MC9S12XE-Family Reference Manual Rev. 1.23
Address
Mode
TRI
Compare with Carry
0
0
0
1
1
0
Machine Code
0
0
RS1
Chapter 10 XGATE (S12XGATEV3)
RS2
CPC
0
1
Cycles
P
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