LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 471

• Manufacturer Part Number: LFEBS12UB
• Description: KIT STUDENT LEARNING S12 DG128
• Manufacturer: Freescale Semiconductor

Specifications of LFEBS12UB

• Architecture: 8/16-bit
• Code Gen Tools Included: Code Warrior
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12D
• Kit Contents: HCS12 DG128 Learning Kit
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 11
S12XE Clocks and Reset Generator (S12XECRGV1)
11.1
This specification describes the function of the Clocks and Reset Generator (S12XECRG).
11.1.1
The main features of this block are:
Freescale Semiconductor
Revision
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
Number
V01.00
V01.01
V01.02
V01.03
V01.04
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
•
•
•
•
Phase Locked Loop (IPLL) frequency multiplier with internal filter
— Reference divider
— Post divider
— Configurable internal filter (no external pin)
— Optional frequency modulation for defined jitter and reduced emission
— Automatic frequency lock detector
— Interrupt request on entry or exit from locked condition
— Self Clock Mode in absence of reference clock
System Clock Generator
— Clock Quality Check
— User selectable fast wake-up from Stop in Self-Clock Mode for power saving and immediate
— Clock switch for either Oscillator or PLL based system clocks
Computer Operating Properly (COP) watchdog timer with time-out clear window.
System Reset generation from the following possible sources:
— Power on reset
— Low voltage reset
Introduction
program execution
Features
20 Nov. 2008
26 Oct. 2005
02 Nov 2006
4 Mar. 2008
1 Sep. 2008
Revision
Date
11.4.1.1/11-488
11.4.1.4/11-491
11.4.3.3/11-495
11.3.2.4/11-477
Table 11-14
Sections
Affected
MC9S12XE-Family Reference Manual , Rev. 1.23
Table 11-1. Revision History
Initial release
Table “Examples of IPLL Divider settings”: corrected $32 to $31
Corrected details
added 100MHz example for PLL
S12XECRG Flags Register: corrected address to Module Base + 0x0003
Description of Changes
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