LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 511

Manufacturer Part Number

KIT STUDENT LEARNING S12 DG128

Manufacturer

Freescale Semiconductor

Architecture

Code Gen Tools Included

Code Warrior

Silicon Manufacturer

Core Architecture

Core Sub-architecture

Silicon Core Number

Silicon Family Name

Kit Contents

HCS12 DG128 Learning Kit

Rohs Compliant

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Writes to this register will abort current conversion sequence.

Read: Anytime

Write: Anytime

Freescale Semiconductor

Module Base + 0x0001

Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers

indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010

ATD Control Register 1 (ATDCTL1)

External Trigger Source Select — This bit selects the external trigger source to be either one of the AD

channels or one of the ETRIG3-0 inputs. See device speciﬁcation for availability and connectivity of ETRIG3-

0 inputs. If a particular ETRIG3-0 input option is not available, writing a 1 to ETRISEL only sets the bit but has

not effect, this means that one of the AD channels (selected by ETRIGCH3-0) is conﬁgured as the source for

external trigger. The coding is summarized in

A/D Resolution Select — These bits select the resolution of A/D conversion results. See

WRAP3 WRAP2 WRAP1 WRAP0

1. If only AN0 should be converted use MULT=0.

Table 13-3. Multi-Channel Wrap Around Coding

Figure 13-4. ATD Control Register 1 (ATDCTL1)

MC9S12XE-Family Reference Manual Rev. 1.23

Table 13-4. ATDCTL1 Field Descriptions

Multiple Channel Conversions (MULT = 1)

Wraparound to AN0 after Converting

Chapter 13 Analog-to-Digital Converter (ADC12B16CV1)