LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 474

Manufacturer Part Number

KIT STUDENT LEARNING S12 DG128

Manufacturer

Freescale Semiconductor

Architecture

Code Gen Tools Included

Code Warrior

Silicon Manufacturer

Core Architecture

Core Sub-architecture

Silicon Core Number

Silicon Family Name

Kit Contents

HCS12 DG128 Learning Kit

Rohs Compliant

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Chapter 11 S12XE Clocks and Reset Generator (S12XECRGV1)

This section provides a detailed description of all registers accessible in the S12XECRG.

2. FORBYP and CTCTL are intended for factory test purposes only.

Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers

indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010

Memory Map and Registers

Module Memory Map

gives an overview on all S12XECRG registers.

is deﬁned at the MCU level and the Address Offset is deﬁned at the module

MC9S12XE-Family Reference Manual , Rev. 1.23

= Unimplemented or Reserved

Figure 11-2. CRG Register Summary

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