LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 248

• Manufacturer Part Number: LFEBS12UB
• Description: KIT STUDENT LEARNING S12 DG128
• Manufacturer: Freescale Semiconductor

Specifications of LFEBS12UB

• Architecture: 8/16-bit
• Code Gen Tools Included: Code Warrior
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12D
• Kit Contents: HCS12 DG128 Learning Kit
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 5 External Bus Interface (S12XEBIV4)
1. All inputs are capable of reducing input threshold level
2. Time-multiplex means that the respective signals share the same pin on chip level and are active alternating in a dedicated
3. Function-multiplex means that one of the respective signals sharing the same pin on chip level continuously uses the pin
248
RE
ADDR[22:20]
ACC[2:0]
ADDR[19:16]
IQSTAT[3:0]
ADDR[15:1]
IVD[15:1]
ADDR0
IVD0
UDS
LSTRB
LDS
RW
WE
CS[3:0]
DATA[15:8]
DATA[7:0]
EWAIT
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
time slot (in modes where applicable).
depending on configuration and reset state.
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Signal
I
(1)
I/O
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
/O
(F)unction
EBI Signal
—
—
—
—
—
—
—
—
—
—
Multiplex
T
T
T
T
(T)ime
Table 5-2. External System Signals Associated with XEBI
(2)
—
—
—
—
—
—
—
—
—
—
—
F
F
F
(3)
MC9S12XE-Family Reference Manual , Rev. 1.23
Read Enable, indicates external read access
External address
Access source
External address
Instruction Queue Status
External address
Internal visibility read data
External address
Internal visibility read data
Upper Data Select, indicates external access
to the high byte DATA[15:8]
Low Strobe, indicates valid data on DATA[7:0]
Lower Data Select, indicates external access
to the low byte DATA[7:0]
Read/Write, indicates the direction of internal
data transfers
Write Enable, indicates external write access
Chip select
Bidirectional data (even address)
Bidirectional data (odd address)
External control for external bus access
stretches (adding wait states)
Description
NS
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
SS
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
Available in Modes
Freescale Semiconductor
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
NX
No
No
No
No
No
No
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
ES
No
No
No
No
No
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
EX
No
No
No
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
ST
No
No
No
No
No
No