LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 628

Manufacturer Part Number

KIT STUDENT LEARNING S12 DG128

Manufacturer

Freescale Semiconductor

Architecture

Code Gen Tools Included

Code Warrior

Silicon Manufacturer

Core Architecture

Core Sub-architecture

Silicon Core Number

Silicon Family Name

Kit Contents

HCS12 DG128 Learning Kit

Rohs Compliant

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Chapter 16 Freescale’s Scalable Controller Area Network (S12MSCANV3)

1. Read: Always reads zero in normal system operation modes

16.3.2.14 MSCAN Miscellaneous Register (CANMISC)

This register provides additional features.

1. Read: Anytime

16.3.2.15 MSCAN Receive Error Counter (CANRXERR)

This register reﬂects the status of the MSCAN receive error counter.

Module Base + 0x000C to Module Base + 0x000D

Module Base + 0x000D

Write: Unimplemented in normal system operation modes

Write: Anytime; write of ‘1’ clears ﬂag; write of ‘0’ ignored

Bus-off State Hold Until User Request — If BORM is set in MSCAN Control Register 1

indicates whether the module has entered the bus-off state. Clearing this bit requests the recovery from bus-off.

0 Module is not bus-off or recovery has been requested by user in bus-off state

1 Module is bus-off and holds this state until user request

Writing to this register when in special system operating modes can alter the

MSCAN functionality.

Section 16.5.2, “Bus-Off

Figure 16-17. MSCAN Miscellaneous Register (CANMISC)

= Unimplemented

Table 16-21. CANMISC Register Field Descriptions

MC9S12XE-Family Reference Manual , Rev. 1.23

Figure 16-16. MSCAN Reserved Register

Recovery,” for details.

Access: User read/write

Freescale Semiconductor