LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 256

• Manufacturer Part Number: LFEBS12UB
• Description: KIT STUDENT LEARNING S12 DG128
• Manufacturer: Freescale Semiconductor

Specifications of LFEBS12UB

• Architecture: 8/16-bit
• Code Gen Tools Included: Code Warrior
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12D
• Kit Contents: HCS12 DG128 Learning Kit
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 5 External Bus Interface (S12XEBIV4)
5.4.2.4.2
5.4.2.4.3
256
DATA[15:0] (external read)
RW
Bus cycle ->
ECLK phase
ADDR[22:20] / ACC[2:0]
ADDR[19:16] / IQSTAT[3:0] ...
ADDR[15:0] / IVD[15:0]
DATA[15:0] (write)
RW
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Bus cycle ->
Bus cycle ->
ECLK phase
ADDR[22:20] / ACC[2:0]
ADDR[19:16] / IQSTAT[3:0] ...
ADDR[15:0] / IVD[15:0]
DATA[15:0] (write)
RW
Bus cycle ->
ECLK phase
ADDR[22:20] / ACC[2:0]
ADDR[19:16] / IQSTAT[3:0] ...
ADDR[15:0] / IVD[15:0]
DATA[15:0] (write)
RW
Write Access Timing
Read-Write-Read Access Timing
Table 5-18. Interleaved Read-Write-Read Accesses (1 Cycle)
...
...
...
...
...
...
...
...
addr 0
high
...
?
1
?
0
MC9S12XE-Family Reference Manual , Rev. 1.23
Table 5-14. Read Access (n–1 Cycles)
Table 5-17. Write Access (n–1 Cycles)
...
...
...
...
...
...
Table 5-16. Write Access (2 Cycles)
...
...
...
...
...
...
1
Table 5-15. Write Access (1 Cycle)
iqstat-1
acc 0
Access #0
addr 0
addr 0
low
1
?
0
z
high
high
Access #0
?
0
?
0
1
1
1
addr 0
iqstat -1
high
iqstat-1
acc 0
acc 0
z
1
0
low
low
Access #0
Access #0
?
0
?
0
data 0
2
iqstat 0
000
addr 0
low
addr 1
z
1
x
0
high
high
Access #1
Access #1
1
0
data 0
data 0
2
2
2
addr 0
iqstat 0
iqstat 0
high
acc 1
z
1
0
000
low
low
x
1
x
0
data 1
3
0000
000
low
addr 2
addr 1
z
1
x
0
high
high
Access #2
Access #1
1
1
Access #2
...
...
...
...
...
...
...
...
3
3
Freescale Semiconductor
iqstat 1
data 2
acc 2
acc 1
0000
3
low
low
data 0
addr 1
x
1
x
x
1
high
1
Access #1
1
...
...
...
...
...
...
...
...
...
...
...
...
...
...
n
acc 1
0000
low
z
1
x
x
1
...
...
...
...
...
...
...
...
...
...