LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 279

• Manufacturer Part Number: LFEBS12UB
• Description: KIT STUDENT LEARNING S12 DG128
• Manufacturer: Freescale Semiconductor

Specifications of LFEBS12UB

• Architecture: 8/16-bit
• Code Gen Tools Included: Code Warrior
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12D
• Kit Contents: HCS12 DG128 Learning Kit
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.5
6.5.1
After system reset, software should:
6.5.2
The interrupt request priority level scheme makes it possible to implement priority based interrupt request
nesting for the I bit maskable interrupt requests handled by the CPU.
I bit maskable interrupt requests cannot be interrupted by other I bit maskable interrupt requests per
default. In order to make an interrupt service routine (ISR) interruptible, the ISR must explicitly clear the
I bit in the CCR (CLI). After clearing the I bit, I bit maskable interrupt requests with higher priority can
interrupt the current ISR.
An ISR of an interruptible I bit maskable interrupt request could basically look like this:
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Initialize the interrupt vector base register if the interrupt vector table is not located at the default
location (0xFF10–0xFFF9).
Initialize the interrupt processing level configuration data registers (INT_CFADDR,
INT_CFDATA0–7) for all interrupt vector requests with the desired priority levels and the request
target (CPU or XGATE module). It might be a good idea to disable unused interrupt requests.
If the XGATE module is used, setup the XGATE interrupt priority register (INT_XGPRIO) and
configure the XGATE module (please refer the XGATE Block Guide for details).
Enable I maskable interrupts by clearing the I bit in the CCR.
Enable the X maskable interrupt by clearing the X bit in the CCR (if required).
I bit maskable interrupt requests can be interrupted by an interrupt request with a higher priority,
so that there can be up to seven nested I bit maskable interrupt requests at a time (refer to
14
Service interrupt, e.g., clear interrupt flags, copy data, etc.
Clear I bit in the CCR by executing the instruction CLI (thus allowing interrupt requests with
higher priority)
Process data
Return from interrupt by executing the instruction RTI
Initialization/Application Information
for an example using up to three nested interrupt requests).
Initialization
Interrupt Nesting
MC9S12XE-Family Reference Manual Rev. 1.23
Chapter 6 Interrupt (S12XINTV2)
Figure 6-
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