LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 84

• Manufacturer Part Number: LFEBS12UB
• Description: KIT STUDENT LEARNING S12 DG128
• Manufacturer: Freescale Semiconductor

Specifications of LFEBS12UB

• Architecture: 8/16-bit
• Code Gen Tools Included: Code Warrior
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12D
• Kit Contents: HCS12 DG128 Learning Kit
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1. 16 bits vector address based
2. For detailed description of XGATE channel ID refer to XGATE Block Guide
Chapter 1 Device Overview MC9S12XE-Family
Vector Address
1.6.3
When a reset occurs, MCU registers and control bits are initialized. Refer to the respective block
descriptions for register reset states.
On each reset, the Flash module executes a reset sequence to load Flash configuration registers and
initialize the buffer RAM EEE partition, if required.
1.6.3.1
On each reset, the Flash module will hold CPU activity while loading Flash module registers and
configuration from the Flash memory. The duration of this phase is given as t
parameter specification. If double faults are detected in the reset phase, Flash module protection and
security may be active on leaving reset. This is explained in more detail in the Flash module section.
1.6.3.2
During this phase of the reset sequence (following on from the core hold phase) the CPU can execute
instructions while the FTM initialization completes and, if configured for EEE operation, the EEE RAM
84
Vector base + $4C
Vector base + $3E
Vector base + $3C
Vector base + $3A
Vector base + $42
Vector base + $16
Vector base + $14
Vector base + $12
Vector base + $10
Vector base+ $4E
Vector base+ $4A
Vector base+ $48
Vector base+ $46
Vector base+ $44
Vector base+ $40
Vector base+ $18
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
to
Effects of Reset
Flash Configuration Reset Sequence (Core Hold Phase)
EEE Reset Sequence Phase (Core Active Phase)
(1)
Channel
XGATE
ID
$1F
$1E
$27
$26
$25
$24
$23
$22
$21
$20
—
—
—
—
(2)
Table 1-14. Interrupt Vector Locations (Sheet 4 of 4)
TIM Pulse accumulator A overflow
TIM Pulse accumulator input edge
MC9S12XE-Family Reference Manual , Rev. 1.23
XGATE software error interrupt
System Call Interrupt (SYS)
ATD0 Compare Interrupt
ATD1 Compare Interrupt
TIM timer channel 3
TIM timer channel 4
TIM timer channel 5
TIM timer channel 6
TIM timer channel 7
MPU Access Error
TIM timer overflow
Spurious interrupt
Interrupt Source
Reserved
Mask
None
None
CCR
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
—
—
ATD0CTL2 (ACMPIE)
ATD1CTL2 (ACMPIE)
PACTL (PAOVI)
Local Enable
TSRC2 (TOF)
PACTL (PAI)
TIE (C3I)
TIE (C4I)
TIE (C5I)
TIE (C6I)
TIE (C7I)
None
None
None
None
RST
in the device electrical
Freescale Semiconductor
Wake up
STOP
Yes
Yes
No
No
No
No
No
No
No
No
No
No
—
—
Wake up
WAIT
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
—
—