LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 124

• Manufacturer Part Number: LFEBS12UB
• Description: KIT STUDENT LEARNING S12 DG128
• Manufacturer: Freescale Semiconductor

Specifications of LFEBS12UB

• Architecture: 8/16-bit
• Code Gen Tools Included: Code Warrior
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12D
• Kit Contents: HCS12 DG128 Learning Kit
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1. Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data source
1. Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data source
Chapter 2 Port Integration Module (S12XEPIMV1)
2.3.19
2.3.20
124
Function
Address 0x0032 (PRR)
Address 0x0033 (PRR)
is depending on the data direction value.
Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
is depending on the data direction value.
Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
Altern.
Field
Reset
Reset
7-0
PK
W
W
R
R
ROMCTL
Port K general purpose input/output data—Data Register
Port K pins 7 through 0 are associated with external bus control signals and internal memory expansion emulation
pins. These include ADDR[22:16], Access Source (ACC[2:0]), External Wait (EWAIT) and instruction pipe signals
IQSTAT[3:0]. Bits 6-0 carry the external addresses in all expanded modes. In emulation modes the address is
multiplexed with the alternate functions ACC and IQSTAT on the respective pins.
When not used with the alternative function, these pins can be used as general purpose I/O.
If the associated data direction bits of these pins are set to 1, a read returns the value of the port register, otherwise
the buffered pin input state is read.
DDRK7
EWAIT
Port K Data Register (PORTK)
Port K Data Direction Register (DDRK)
PK7
or
0
0
7
7
ADDR22
DDRK6
ACC2
PK6
mux
0
0
6
6
Figure 2-18. Port K Data Direction Register (DDRK)
Table 2-18. PORTK Register Field Descriptions
MC9S12XE-Family Reference Manual , Rev. 1.23
Figure 2-17. Port K Data Register (PORTK)
ADDR21
DDRK5
ACC1
PK5
mux
0
0
5
5
ADDR20
DDRK4
ACC0
PK4
mux
0
0
4
4
Description
IQSTAT3
ADDR19
DDRK3
PK3
mux
3
0
3
0
IQSTAT2
ADDR18
DDRK2
PK2
mux
0
0
2
2
IQSTAT1
Access: User read/write
Access: User read/write
ADDR17
Freescale Semiconductor
DDRK1
PK1
mux
0
0
1
1
IQSTAT0
ADDR16
DDRK0
PK0
mux
0
0
0
0
(1)
(1)