LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 239

Manufacturer Part Number

KIT STUDENT LEARNING S12 DG128

Manufacturer

Freescale Semiconductor

Architecture

Code Gen Tools Included

Code Warrior

Silicon Manufacturer

Core Architecture

Core Sub-architecture

Silicon Core Number

Silicon Family Name

Kit Contents

HCS12 DG128 Learning Kit

Rohs Compliant

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Read: Anytime

Write: Anytime

Read: Anytime

Write: Anytime

Freescale Semiconductor

Address: Module Base + 0x0008

Address: Module Base + 0x0009

Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers

indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010

MPU Descriptor Register 2 (MPUDESC2)

MPU Descriptor Register 3 (MPUDESC3)

Memory range lower boundary address bits — The LOW_ADDR[18:11] bits represent bits [18:11] of the

global memory address that is used as the lower boundary for the described memory range.

Memory range lower boundary address bits — The LOW_ADDR[10:3] bits represent bits [10:3] of the global

memory address that is used as the lower boundary for the described memory range.

Write-Protect bit — The WP bit causes the described memory range to be treated as write-protected. If this

bit is set every attempt to write in the described memory range causes an access violation.

Figure 4-10. MPU Descriptor Register 2 (MPUDESC2)

Figure 4-11. MPU Descriptor Register 3 (MPUDESC3)

MC9S12XE-Family Reference Manual Rev. 1.23

Table 4-10. MPUDESC2 Field Descriptions

Table 4-11. MPUDESC3 Field Descriptions

Table 4-9. MPUDESC1 Field Descriptions

LOW_ADDR[10:3]

Chapter 4 Memory Protection Unit (S12XMPUV1)

HIGH_ADDR[22:19]