LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 472

• Manufacturer Part Number: LFEBS12UB
• Description: KIT STUDENT LEARNING S12 DG128
• Manufacturer: Freescale Semiconductor

Specifications of LFEBS12UB

• Architecture: 8/16-bit
• Code Gen Tools Included: Code Warrior
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12D
• Kit Contents: HCS12 DG128 Learning Kit
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 11 S12XE Clocks and Reset Generator (S12XECRGV1)
11.1.2
This subsection lists and briefly describes all operating modes supported by the S12XECRG.
11.1.3
Figure 11-1
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indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
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— Illegal address reset
— COP reset
— Loss of clock reset
— External pin reset
Real-Time Interrupt (RTI)
Run Mode
All functional parts of the S12XECRG are running during normal Run Mode. If RTI or COP
functionality is required the individual bits of the associated rate select registers (COPCTL,
RTICTL) have to be set to a non zero value.
Wait Mode
In this mode the IPLL can be disabled automatically depending on the PLLWAI bit.
Stop Mode
Depending on the setting of the PSTP bit Stop Mode can be differentiated between Full Stop Mode
(PSTP = 0) and Pseudo Stop Mode (PSTP = 1).
— Full Stop Mode
— Pseudo Stop Mode
Self Clock Mode
Self Clock Mode will be entered if the Clock Monitor Enable Bit (CME) and the Self Clock Mode
Enable Bit (SCME) are both asserted and the clock monitor in the oscillator block detects a loss of
clock. As soon as Self Clock Mode is entered the S12XECRG starts to perform a clock quality
check. Self Clock Mode remains active until the clock quality check indicates that the required
quality of the incoming clock signal is met (frequency and amplitude). Self Clock Mode should be
used for safety purposes only. It provides reduced functionality to the MCU in case a loss of clock
is causing severe system conditions.
The oscillator is disabled and thus all system and core clocks are stopped. The COP and the
RTI remain frozen.
The oscillator continues to run and most of the system and core clocks are stopped. If the
respective enable bits are set the COP and RTI will continue to run, else they remain frozen.
Modes of Operation
Block Diagram
shows a block diagram of the S12XECRG.
MC9S12XE-Family Reference Manual , Rev. 1.23
Freescale Semiconductor