UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 181

• Manufacturer Part Number: UPD70F3738GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3738GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(b) Cautions on alternate-function mode (input)
The signal input to the alternate-function block is low level when the PMCn.PMCnm bit is 0 due to the
ANDed output of the PMCn register set value and the pin level. Thus, depending on the port setting and
alternate-function operation enable timing, an unexpected operation may occur. Therefore, switch between
the port mode and alternate-function mode in the following sequence.
• Switching from port mode to alternate-function mode (input)
• Switching from alternate-function mode (input) to port mode
Specific examples are shown below.
[Example 1] Switching from general-purpose port pin (P02) to external interrupt pin (NMI)
Set the pins to the alternate-function mode using the PMCn register and then enable the alternate-
function operation.
Stop the alternate-function operation and then switch the pins to the port mode.
The setting order that may cause a malfunction when switching from the P41 pin function to the
SCL01 pin function is shown below.
In <2>, I
to the pin. In the CMOS output period of <2> or <3>, an unnecessary current may be
generated.
<1>
<2>
<3>
<4>
Setting Order
When the P02/NMI pin is pulled up as shown in Figure 4-33 and the rising edge is specified
by the NMI pin edge detection setting, even though a high level is input continuously to the
NMI pin while switching from the P02 pin to the NMI pin (PMC02 bit = 0 → 1), this is
detected as a rising edge, as if the low level changed to a high level, and an NMI interrupt
occurs.
To avoid this, set the NMI pin’s valid edge after switching from the P02 pin to the NMI pin.
2
C communication may be affected since the alternate-function SOB0 output is output
Initial value
(PMC41 bit = 0,
PFC41 bit = 0,
PF41 bit = 0)
PMC41 bit ← 1
PFC41 bit ← 1
PF41 bit ← 1
CHAPTER 4 PORT FUNCTIONS
Setting
User’s Manual U18953EJ5V0UD
Port mode (input)
SOB0 output
SCL01 I/O
SCL01 I/O
Pin State
Hi-Z
Low level (may be high level depending
on the CSIB0 setting)
High level (CMOS output)
Hi-Z (N-ch open-drain output)
Pin Level
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