UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 226

• Manufacturer Part Number: UPD70F3738GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3738GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

6.5.2
224
(1) PLL control register (PLLCTL)
Cautions 1. When the PLLON bit is cleared to 0, the SELPLL bit is automatically cleared to 0 (clock-
Cautions 1. The PLL mode cannot be used when f
(2) Clock control register (CKC)
The PLLCTL register is an 8-bit register that controls the PLL function.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 01H.
The CKC register is a special register. Data can be written to this register only in a combination of specific
sequences (see 3.4.7 Special registers).
The CKC register controls the internal system clock in the PLL mode.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 0AH.
Registers
2. The SELPLL bit can be set to 1 only when the PLL clock frequency is stabilized. If not (if
2. Be sure to set the CKC register to 0AH. If a value other than 0AH is set, the operation is
PLLCTL
After reset:
CKC
through mode).
the PLL is unlocked), “0” is written to the SELPLL bit whatever data is written to it.
not guaranteed.
After reset: 01H
CKDIV0
SELPLL
PLLON
0AH
0
0
1
0
1
0
1
0
f
Setting prohibited
XX
Clock-through mode
PLL mode
Disable PLL operation
Enable PLL operation
(After PLL operation starts, a lockup time is required for frequency stabilization.)
R/W
R/W
= 4 × f
0
0
CHAPTER 6 CLOCK GENERATOR
X
(f
Address:
Internal system clock (f
Address: FFFFF82CH
X
User’s Manual U18953EJ5V0UD
= 2.5 to 5.0 MHz)
0
0
Selection of CPU operation clock mode
FFFFF822H
0
Control of PLL operation
X
0
= 5.0 to 10.0 MHz.
XX
1
) in PLL mode
0
0
0
SELPLL
< >
1
CKDIV0
PLLON
< >