UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 576

• Manufacturer Part Number: UPD70F3738GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3738GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

574
RXDAn (input)
Reception interrupt
(INTUAnR)
Edge detection
Capture timer
Notes 1. The wakeup signal is detected by the pin edge detector, UARTAn is enabled, and the SBF reception
2. Reception is performed until detection of the stop bit. Upon detection of SBF reception of 11 or more
3. If SBF reception ends normally, an interrupt request signal is output. The timer is enabled by an SBF
4. The RXDAn pin is connected to TI (capture input) of the timer and the transfer rate is calculated. The
5. A check-sum field is identified by software. UARTAn is initialized following reception of the check-
LIN
bus
mode is set.
bits, it is judged as normal SBF reception end, and an interrupt signal is output. Upon detection of
SBF reception of less than 11 bits, it is judged as an SBF reception error, no interrupt signal is
output, and the mode returns to the SBF reception mode.
reception complete interrupt. Moreover, error detection for the UAnSTR.UAnOVE, UAnSTR.UAnPE,
and UAnSTR.UAnFE bits is suppressed and UART communication error detection processing and
data transfer of the UARTAn receive shift register and UAnRX register is not performed. The
UARTAn receive shift register holds the initial value, FFH.
value of the UAnCTL2 register obtained by correcting the baud rate error after UARTA enable goes
low is set again, causing the status to become the reception status.
sum field, and the processing for re-specifying the SBF reception mode is performed, also by
software.
Disable
Wake-up
signal
frame
CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE A (UARTA)
Enable
Note 1
Figure 16-12. LIN Reception Format
field (SBF)
reception
Disable
Note 2
break
SBF
Sync
User’s Manual U18953EJ5V0UD
Note 3
Enable
SF reception
Note 4
Sync
field
ID reception
field
ID
reception
DATA
Data
field
reception
DATA
Data
field
reception
Check
SUM
Note 5
field
Data