UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 712

• Manufacturer Part Number: UPD70F3738GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3738GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

19.6.7 Wait state cancellation method
communication.
conflict between the SDA0n line change timing and the IICn register write timing may result in the data output to the
SDA0n line being incorrect.
communication, enabling the wait state to be cancelled.
enabling the wait state to be cancelled.
710
In the case of I
• By writing data to the IICn register
• By setting the IICCn.WRELn bit to 1 (wait state cancellation)
• By setting the IICCn.STTn bit to 1 (start condition generation)
• By setting the IICCn.SPTn bit to 1 (stop condition generation)
If any of these wait state cancellation actions is performed, I
When canceling the wait state and sending data (including addresses), write data to the IICn register.
To receive data after canceling the wait state, or to complete data transmission, set the WRELn bit to 1.
To generate a restart condition after canceling the wait state, set the STTn bit to 1.
To generate a stop condition after canceling the wait state, set the SPTn bit to 1.
Cancel each wait state only once.
For example, if data is written to the IICn register following wait state cancellation by setting the WRELn bit to 1, a
Even in other operations, if communication is stopped halfway, clearing the IICCn.IICEn bit to 0 will stop
If the I
2
C bus deadlocks due to noise, etc., setting the IICCn.LRELn bit to 1 causes the communication to stop,
2
C0n, a wait state can be canceled normally in the following ways (n = 0 to 2).
User’s Manual U18953EJ5V0UD
CHAPTER 19 I
2
C BUS
2
C0n will cancel the wait state and restart