UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 240

• Manufacturer Part Number: UPD70F3738GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3738GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

238
(2) TMPn control register 1 (TPnCTL1)
The TPnCTL1 register is an 8-bit register that controls the operation of TMPn.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
(n = 0 to 5)
TPnCTL1
After reset: 00H
Cautions 1. The TPnEST bit is valid only in the external trigger pulse output
TPnEST
TPnEEE
TPnMD2
0
1
0
1
7
0
0
0
0
0
1
1
1
1
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP)
Disable operation with external event count input.
(Perform counting with the internal count clock selected by the
TPnCTL0.TPnCK0 to TPnCK2 bits.)
Generate a valid signal for external trigger input.
• In one-shot pulse output mode: A one-shot pulse is output with writing
• In external trigger pulse output mode: A PWM waveform is output with
Enable operation with external event count input.
(Perform counting at the valid edge of the external event count input
signal.)
2. External event count input is selected in the external event count
3. Set the TPnEEE and TPnMD2 to TPnMD0 bits when the timer
TPnEST TPnEEE
TPnMD1
4. Be sure to clear bits 3, 4, and 7 to “0”.
R/W
<6>
mode or the one-shot pulse output mode.
writing 1 to this bit is ignored.
mode regardless of the value of the TPnEEE bit.
operation is stopped (TPnCTL0.TPnCE bit = 0). (The same value can
be written when the TPnCE bit = 1.) The operation is not guaranteed
when rewriting is performed with the TPnCE bit = 1. If rewriting was
mistakenly performed, clear the TPnCE bit to 0 and then set the bits
again.
0
0
1
1
0
0
1
1
Address: TP0CTL1 FFFFF591H, TP1CTL1 FFFFF5A1H,
User’s Manual U18953EJ5V0UD
TPnMD0
<5>
0
1
0
1
0
1
0
1
TP2CTL1 FFFFF5B1H, TP3CTL1 FFFFF5C1H,
TP4CTL1 FFFFF5D1H, TP5CTL1 FFFFF5E1H
Interval timer mode
External event count mode
External trigger pulse output mode
One-shot pulse output mode
PWM output mode
Free-running timer mode
Pulse width measurement mode
Setting prohibited
4
0
Software trigger control
Count clock selection
1 to the TPnEST bit as the trigger.
3
0
−
Timer mode selection
writing 1 to the TPnEST bit as the
trigger.
TPnMD2 TPnMD1 TPnMD0
2
1
In any other mode,
0