UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 944

• Manufacturer Part Number: UPD70F3738GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3738GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

942
• Port registers when UARTA0 is used
• Port registers when CSIB0 is used
When UARTA0 is used, port registers are set by the debug monitor program to make the TXDA0 and
RXDA0 pins valid. Do not change the following register settings in the user program during debugging. (The
same value can be written again.)
When CSIB0 is used, port registers are set by the debug monitor program to make the SIB0, SOB0, SCKB0,
and HS (PCM0) pins valid.
debugging. (The same value can be written again.)
(a) SIB0, SOB0, and SCKB0 settings
(b) HS (PCM0 pin) settings
Remark ×: don’t care
Note Writing to this bit is prohibited.
Remark ×: don’t care
PMC3L
PFC3
PMCM
PMC4
PFC4
The port values corresponding to the HS pin are changed by the monitor program according to
the debugger status. To specify port register settings in 8-bit units, read-modify-write can usually
be used in the user program. If an interrupt for debugging occurs before writing, however, an
unexpected operation may be performed.
PCM
×
7
×
7
7
×
7
×
7
×
7
×
×
6
×
6
CHAPTER 31 ON-CHIP DEBUG FUNCTION
6
×
6
6
×
×
6
×
Do not change the following register settings in the user program during
×
5
×
5
User’s Manual U18953EJ5V0UD
5
5
×
5
×
5
×
×
4
×
4
×
4
4
×
4
×
4
×
×
3
3
×
×
3
×
3
×
3
3
×
×
2
2
×
×
2
2
×
2
1
2
×
×
1
0
1
1
1
0
1
1
1
1
×
×
0
0
0
1
Note
0
0
0
1
0
0
0