UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 561

• Manufacturer Part Number: UPD70F3738GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3738GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

<R>
(n = 0 to 5)
UAnSTR
After reset: 00H
CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE A (UARTA)
Note
UAnOVE
The UAnTSF bit is always 1 when performing continuous transmission. When
initializing the transmission unit, check that the UAnTSF bit is 0 before performing
initialization. The transmit data is not guaranteed when initialization is performed
while the UAnTSF bit is 1.
• The operation of the UAnPE bit is controlled by the settings of the
• Once the UAnPE bit is set (1), the value is retained until the bit is cleared (0).
• The UAnPE bit can be read and written, but it can only be cleared by writing 0 to it;
• Only the first bit of the receive data stop bits is checked, regardless of the value
• Once the UAnFE bit is set (1), the value is retained until the bit is cleared (0).
• The UAnFE bit can be both read and written, but it can only be cleared by
• When an overrun error occurs, the data is discarded without the next receive data
• Once the UAnOVE bit is set (1), the value is retained until the bit is cleared (0).
• The UAnOVE bit can be both read and written, but it can only be cleared by writing
UAnTSF
UAnTSF
UAnPE
UAnFE
UAnCTL0.UAnPS1 and UAnCTL0.UAnPS0 bits.
it cannot be set by writing 1 to it. When 1 is written to this bit, the previous value is
retained.
of the UAnCTL0.UAnSL bit.
writing 0 to it; it cannot be set by writing 1 to it. When 1 is written to this bit, the
previous value is retained.
being written to the receive buffer.
0 to it; it cannot be set by writing 1 to it. When 1 is written to this bit, the previous
value is retained.
<7>
μ
0
1
0
1
0
1
0
1
PD70F3792, 70F3793 only
The transmit shift register does not have data.
The transmit shift register has data.
(Write to UAnTX register)
• When the UAnPWR bit or the UAnRXE bit has been set to 0.
• When 0 has been written
The received parity bit does not match the specified parity.
• When the UAnPWR bit or the UAnRXE bit has been set to 0
• When 0 has been written
When no stop bit is detected during reception
• When the UAnPWR bit or the UAnRXE bit has been set to 0.
• When 0 has been written
When receive data has been set to the UAnRX register and the next
receive operation is completed before that receive data has been read
R/W
• When the UAnPWR bit or the UAnTXE bit has been set to 0.
• When, following transfer completion, there was no next data transfer
from UAnTX register
6
0
User’s Manual U18953EJ5V0UD
Address: UA0STR FFFFFA04H, UA1STR FFFFFA14H,
5
0
UA2STR FFFFFA24H, UA3STR FFFFFA34H
UA4STR FFFFFA44H
4
0
Transfer status flag
Overrun error flag
Framing error flag
Parity error flag
3
0
Note
UAnPE
, UA5STR FFFFFA54H
<2>
UAnFE
<1>
Note
UAnOVE
,
Note
<0>
559