UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 560

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UPD70F3738GF-GAS-AX

Manufacturer Part Number
UPD70F3738GF-GAS-AX
Description
MCU 32BIT V850ES/JX3-L 100-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Lr
Datasheet

Specifications of UPD70F3738GF-GAS-AX

Core Processor
RISC
Core Size
32-Bit
Speed
20MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
84
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
UPD70F3738GF-GAS-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
558
(5) UARTAn status register (UAnSTR)
The UAnSTR register is an 8-bit register that displays the UARTAn transfer status and reception error contents.
This register can be read or written in 8-bit or 1-bit units, but the UAnTSF bit is a read-only bit, while the
UAnPE, UAnFE, and UAnOVE bits can be both read and written. However, these bits can only be cleared by
writing 0; they cannot be set by writing 1 (even if 1 is written to them, the previous value is retained).
The conditions for clearing the UAnSTR register are shown below.
UAnSTR register
UAnTSF bit
UAnPE, UAnFE, UAnOVE bits
UAnSLS2
UAnRDL
This register can be set when the UAnPWR bit or the UAnTXE bit is 0.
UAnTDL
• The output level of the TXDAn pin can be inverted by using the UAnTDL bit.
• This register can be set when the UAnPWR bit or the UAnTXE bit is 0.
• The input level of the RXDAn pin can be inverted by using the UAnRDL bit.
• This register can be set when the UAnPWR bit or the UAnRXE bit is 0.
1
1
1
0
0
0
0
1
0
1
0
1
CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE A (UARTA)
UAnSLS1
Normal output of transfer data
Inverted output of transfer data
Normal input of transfer data
Inverted input of transfer data
Register/Bit
Table 16-3. Conditions for Clearing STR Register
0
1
1
0
0
1
1
0
UAnSLS0
1
0
1
0
1
0
1
0
User’s Manual U18953EJ5V0UD
13-bit output (initial value)
14-bit output
15-bit output
16-bit output
17-bit output
18-bit output
19-bit output
20-bit output
Transmit data level bit
Receive data level bit
• Reset
• UAnCTL0.UAnPWR = 0
• UAnCTL0.UAnTXE = 0
• 0 write
• UAnCTL0.UAnRXE = 0
SBF transmit length selection
Conditions for Clearing
(2/2)

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