UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 594

• Manufacturer Part Number: UPD70F3738GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3738GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

17.4 Registers
592
(1) UARTC0 control register 0 (UC0CTL0)
The UC0CTL0 register is an 8-bit register that controls the UARTC0 serial transfer operation.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 10H.
CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) (
UC0CTL0
After reset: 10H
UC0PWR
UC0PWR
UC0RXE
The UARTC0 operation is controlled by the UC0PWR bit. The TXDC0 pin output
is fixed to high level by clearing the UC0PWR bit to 0 (fixed to low level if
UC0OPT0.UC0TDL bit = 1).
UC0TXE
• To start transmission, set the UC0PWR bit to 1 and then set the UC0TXE bit to 1.
• To initialize the transmission unit, clear the UC0TXE bit to 0, wait for two cycles of
• When UARTC0 operation is enabled (UC0PWR bit = 1) and the UC0TXE bit is set
• To start reception, set the UC0PWR bit to 1 and then set the UC0RXE bit to 1.
• To initialize the reception unit, clear the UC0RXE bit to 0, wait for two cycles of
• When UARTC0 operation is enabled (UC0PWR bit = 1) and the UC0RXE bit is set
To stop transmission, clear the UC0TXE bit to 0 and then UC0PWR bit to 0.
the base clock, and then set the UC0TXE bit to 1 again. Otherwise, initialization
may not be executed (for the base clock, see 17.7 (1) (a) Base clock).
to 1, transmission is enabled after at least two cycles of the base clock (f
elapsed.
To stop reception, clear the UC0RXE bit to 0 and then UC0PWR bit to 0.
the base clock, and then set the UC0RXE bit to 1 again. Otherwise, initialization
may not be executed (for the base clock, see 17.7 (1) (a) Base clock).
to 1, reception is enabled after at least two cycles of the base clock (f
elapsed. If a start bit is received before reception is enabled, the start bit is
ignored.
<7>
0
1
0
1
0
1
Disable UARTC0 operation (UARTC0 reset asynchronously)
Enable UARTC0 operation
Disable transmission operation
Enable transmission operation
Disable reception operation
Enable reception operation
R/W
UC0TXE UC0RXE UC0DIR UC0PS1 UC0PS0
<6>
Address: FFFFFAA0H
User’s Manual U18953EJ5V0UD
<5>
Transmission operation enable
Reception operation enable
UARTC0 operation control
<4>
3
2
PD70F3792, 70F3793)
UC0CL
1
UCLK
UCLK
) have
UC0SL
) have
0
(1/2)