UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 298

• Manufacturer Part Number: UPD70F3738GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3738GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

outputs a PWM waveform from the TOPn1 pin.
newly written value is reflected when the value of the 16-bit counter matches the value of the CCR0 buffer register and
the 16-bit counter is cleared to 0000H.
time after its count value matches the value of the CCR0 buffer register, and the 16-bit counter is cleared to 0000H.
The INTTPnCC1 compare match interrupt request signal is generated when the value of the 16-bit counter matches
the value of the CCR1 buffer register.
296
When the TPnCE bit is set to 1, the 16-bit counter is cleared from FFFFH to 0000H, starts incrementing, and
The active level width, cycle, and duty factor of the PWM waveform can be calculated as follows:
The PWM waveform can be changed by rewriting the TPnCCRa register while the counter is incrementing. The
The INTTPnCC0 compare match interrupt request signal is generated when the 16-bit counter increments next
Remark
Active level width = (Set value of TPnCCR1 register) × Count clock cycle
Cycle = (Set value of TPnCCR0 register + 1) × Count clock cycle
Duty factor = (Set value of TPnCCR1 register)/(Set value of TPnCCR0 register + 1)
CCR0 buffer register
CCR1 buffer register
INTTPnCC1 signal
a = 0, 1
n = 0 to 5
TPnCCR0 register
TPnCCR1 register
NTTPnCC0 signal
TOPn0 pin output
TOPn1 pin output
16-bit counter
TPnCE bit
FFFFH
0000H
Figure 7-45. Basic Timing of Operations in PWM Output Mode
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP)
Active period
D
(D
10
D
10
User’s Manual U18953EJ5V0UD
00
)
(D
D
D
Cycle
00
10
D
00
D
D
10
10
D
+ 1)
00
00
D
Inactive period
(D
10
D
00
00
− D
10
+ 1)
D
D
11
01
D
01
D
D
D
D
11
11
01
11
D
01