UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 27

• Manufacturer Part Number: UPD70F3738GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3738GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

<R>
1.2
Note
Minimum instruction execution time: 50 ns (operating on main clock (f
General-purpose registers:
CPU features:
Memory space:
Interrupts and exceptions:
Ports:
Features
μ
PD70F3792, 70F3793 only
• Internal memory:
• External bus interface: Separate bus/multiplexed bus output selectable
μ
μ
μ
μ
PD70F3737
PD70F3738
PD70F3792
PD70F3793
32 bits × 32 registers
Signed multiplication (16 × 16 → 32): 1 to 2 clocks
Signed multiplication (32 × 32 → 64): 1 to 5 clocks
Saturated operations (overflow and underflow detection functions included)
Most instructions can be executed in 1 clock cycle by using 32-bit RISC-based 5-
stage pipeline architecture
Instruction fetching from internal ROM and accessing internal RAM for data can
be executed separately, by using Harvard architecture
High code efficiency achieved by using variable length instructions
32-bit shift instruction: 1 clock cycle
Bit manipulation instructions
Load/store instructions with long/short format
64 MB of linear address space (for programs and data)
External expansion: Up to 16 MB (including 1 MB used as internal ROM/RAM)
Software exceptions:
Exception trap:
I/O ports:
maskable
1
1
1
1
Non-
200 ns (operating on main clock (f
400 ns (operating on main clock (f
30.5
CHAPTER 1 INTRODUCTION
RAM:
Flash memory: 128/256/384/512 KB (see Table 1-1)
8/16 bit data bus sizing function
Wait function
• Programmable wait function
• External wait function
Idle state function
Bus hold function
User’s Manual U18953EJ5V0UD
μ
s (operating on subclock (f
Internal
maskable
47
47
54
54
84 (
83 (
μ
μ
PD70F3737, 70F3738)
PD70F3792, 70F3793)
8/16/32/40 KB (see Table 1-1)
total
48
48
55
55
32 sources
2 sources
maskable
1
1
1
1
Non-
XX
XT
XX
XX
) of 20 MHz: V
) of 32.768 kHz)
) of 5 MHz: V
) of 2.5 MHz: V
external
maskable
8
8
8
8
DD
DD
DD
= 2.7 to 3.6 V)
= 2.2 to 3.6 V)
total
9
9
9
9
= 2.0 to 3.6 V)
Note
25