UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 268

• Manufacturer Part Number: UPD70F3738GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3738GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

7.4.2
TPnCTL0.TPnCE bit is set to 1, and an interrupt request signal (INTTPnCC0) is generated each time the specified
number of edges have been counted. The timer output pins (TOPn0 and TOPn1) cannot be used. To use the TOPn1
pin in the external event count mode, first set the TPnCTL1.TPnEEE bit to 1 in the interval timer mode (see 7.4.1 (3)
Operation of interval timer based on input of external event count).
increments each time the valid edge of the external event count input is detected, and the value of the TPnCCR0
register is transferred to the CCR0 buffer register.
0000H, and a compare match interrupt request signal (INTTPnCC0) is generated.
the specified number of times (that is, the value of the TPnCCR0 register + 1).
266
TIPn0 pin
(external event
count input)
In the external event count mode, the valid edge of the external event count input is counted when the
Usually, the TPnCCR1 register is not used in the external event count mode.
Remarks 1. For how to set the TIPn0 pin, see Table 7-2 Pins Used by TMPn and Table 4-15 Settings When
When the TPnCE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H. The counter
When the value of the 16-bit counter matches the value of the CCR0 buffer register, the 16-bit counter is cleared to
The INTTPnCC0 signal is generated each time the valid edge of the external event count input has been detected
External event count mode (TPnMD2 to TPnMD0 bits = 001)
Remark
2. For how to enable the INTTPnCC0 interrupt signal, see CHAPTER 21 INTERRUPT SERVICING/
Pins Are Used for Alternate Functions.
EXCEPTION PROCESSING.
Figure 7-17. Configuration of Interval Timer in External Event Count Mode
n = 0 to 5
Edge
detector
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP)
TPnCE bit
User’s Manual U18953EJ5V0UD
CCR0 buffer register
TPnCCR0 register
16-bit counter
Clear
Match signal
INTTPnCC0 signal