UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 738

• Manufacturer Part Number: UPD70F3738GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3738GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

19.14 Communication Reservation
19.14.1 When communication reservation function is enabled (IICFn.IICRSVn bit = 0)
reservation can be made to enable transmission of a start condition when the bus is released. There are two modes in
which the bus is not used by the V850ES/JG3-L.
generated and a wait status is set after the bus is released (after a stop condition is detected).
address transfer to start. At this point, the IICCn.SPIEn bit should be set to 1 (n = 0 to 2).
determined according to the bus status (n = 0 to 2).
period, then check the IICSn.MSTSn bit (n = 0 to 2).
the SMCn, CLn1, and CLn0 bits of the IICCLn register and the IICXn.CLXn bit (n = 0 to 2).
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To start master device communications when the V850ES/JG3-L is not currently using the bus, a communication
• When arbitration results in the V850ES/JG3-L being neither the master nor a slave
• When an extension code is received and slave operation is disabled (ACK is not returned and the bus was
If the IICCn.STTn bit is set to 1 while the bus is not used by the V850ES/JG3-L, a start condition is automatically
When the bus release is detected (when a stop condition is detected), writing to the IICn register causes master
When STTn has been set to 1, the operation mode (as start condition or as communication reservation) is
If the bus has been released .............................................A start condition is generated
If the bus has not been released (standby mode)..............Communication reservation
To detect which operation mode has been determined for the STTn bit, set the STTn bit to 1, wait for the wait
The wait periods, which should be set via software, are listed in Table 19-6. These wait periods can be set by using
released when the IICCn.LRELn bit was set to 1) (n = 0 to 2).
User’s Manual U18953EJ5V0UD
CHAPTER 19 I
2
C BUS