UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 290

• Manufacturer Part Number: UPD70F3738GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3738GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

cleared from FFFFH to 0000H, starts incrementing, and outputs a one-shot pulse from the TOPn1 pin. After the one-
shot pulse is output, the 16-bit counter is set to 0000H, stops incrementing, and waits for a trigger. If a trigger is
generated again while the one-shot pulse is being output, it is ignored.
time after its value matches the value of the CCR0 buffer register. The INTTPnCC1 compare match interrupt request
signal is generated when the value of the 16-bit counter matches the value of the CCR1 buffer register.
is used as the trigger.
288
When the TPnCE bit is set to 1, TMPn waits for a trigger. When the trigger is generated, the 16-bit counter is
The output delay period and active level width of the one-shot pulse can be calculated as follows:
The INTTPnCC0 compare match interrupt request signal is generated when the 16-bit counter increments next
Either the valid edge of the external trigger input signal or setting the software trigger (TPnCTL1.TPnEST bit) to 1
Remark
External trigger input
TOPn0 pin output
INTTPnCC0 signal
INTTPnCC1 signal
TPnCCR0 register
TPnCCR1 register
Output delay period = (Set value of TPnCCR1 register) × Count clock cycle
Active level width = (Set value of TPnCCR0 register − Set value of TPnCCR1 register + 1) × Count clock cycle
TOPn1 pin output
(TIPn0 pin input)
Note The output from the TOPn0 pin can also be used as the input to the TIPn0 pin. When using the
16-bit counter
TPnCE bit
n = 0 to 5
output from the TOPn0 pin as the input to the TIPn0 pin, use a software trigger instead of an
external trigger.
FFFFH
0000H
Note
Figure 7-39. Basic Timing of Operations in One-Shot Pulse Output Mode
Wait
for
trigger
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP)
Delay
(D
D
1
1
)
Active
level width
(D
D
User’s Manual U18953EJ5V0UD
0
0
− D
1
+ 1)
Delay
(D
D
1
1
)
Active
level width
(D
D
D
D
0
0
1
0
− D
1
+ 1)
Delay
(D
D
1
1
)
Active
level width
(D
D
0
0
− D
1
+ 1)