UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 271

• Manufacturer Part Number: UPD70F3738GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3738GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(e) TMPn counter read buffer register (TPnCNT)
(f) TMPn capture/compare register 0 (TPnCCR0)
(g) TMPn capture/compare register 1 (TPnCCR1)
The value of the 16-bit counter can be read by reading this register.
When the TPnCCR0 register is set to D
signal (INTTPnCC0) is generated when the number of external events reaches (D
The TPnCCR1 register is not usually used in the external event count mode. However, because the set
value of the TPnCCR1 register is transferred to the CCR1 buffer register and a compare match interrupt
request signal (INTTPnCC1) is generated when the value of the 16-bit counter matches the value of the
CCR1 buffer register, interrupts from this register must be masked by setting the interrupt mask flag
(TPnCCMK1).
Cautions 1. Do not set the TPnCCR0 register to 0000H in the external event count mode.
Remarks 1. TMPn I/O control register 1 (TPnIOC1) and TMPn option register 0 (TPnOPT0) are not
2. Timer output cannot be used in the external event count mode. When using the
2. n = 0 to 5
Figure 7-19. Register Settings in External Event Count Mode (2/2)
timer output based on the input of an external event count, first set the operating
mode to interval mode, and then specify “operation enabled” for the external event
count input (by setting the TPnCTL1.TPnMD2 to TPnMD0 bits to 0, 0, 0 and setting
the TPnCTL1.TPnEEE bit to 1). For details, see 7.4.1 (3) Operation of interval timer
based on input of external event count.
used in the external event count mode.
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP)
User’s Manual U18953EJ5V0UD
0
, the counter is cleared and a compare match interrupt request
0
+ 1).
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