UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 205

• Manufacturer Part Number: UPD70F3738GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3738GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

5.8.2
5.8.3
even if the HLDRQ pin is asserted.
status is entered. When the HLDRQ pin is later deasserted, the HLDAK pin is also deasserted, and the bus hold
status is exited.
The bus hold status transition procedure is shown below.
Because the internal system clock is stopped in the STOP and IDLE modes, the bus hold status is not entered
In the HALT mode, the HLDAK pin is asserted as soon as the HLDRQ pin has been asserted, and the bus hold
<1> A low level signal is input to the HLDRQ pin.
<2> All bus cycle start requests are inhibited.
<3> End of the current bus cycle.
<4> Shift to the bus idle status.
<5> A low level signal is output from the HLDAK pin.
<6> A high level signal is input to the HLDRQ pin.
<7> A high level signal is output from the HLDAK pin.
<8> Bus cycle start request inhibition is released.
<9> The bus cycle starts.
Bus hold procedure
Operation in power save mode
HLDAK (output)
HLDRQ (input)
CHAPTER 5 BUS CONTROL FUNCTION
<1> <2>
User’s Manual U18953EJ5V0UD
<3><4>
<5>
Normal status
Bus hold status
Normal status
<6>
<7><8><9>
203