UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 225

• Manufacturer Part Number: UPD70F3738GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3738GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

6.4.2
control register of port CM.
clock when it is in the operable status. It outputs a low level in the stopped status. However, the CLKOUT pin is in
the port mode (PCM1 pin: input mode) after reset and until it is set in the output mode. Therefore, the status of the pin
is Hi-Z.
6.4.3
open. Set the PCC.MFRC bit to 1 (on-chip feedback resistor not used). Note, however, that time is required to
stabilize the oscillator signal even when inputting an external clock signal.
6.5
6.5.1
unmultiplied clock (clock-through mode) can be selected as the operating clock of the CPU and on-chip peripheral
functions.
The clock output function is used to output the internal system clock (f
The internal system clock (f
The CLKOUT pin functions alternately as the PCM1 pin and functions as a clock output pin if so specified by the
The status of the CLKOUT pin is the same as the internal system clock in Table 6-1 and the pin can output the
An external clock signal can be directly input to the oscillator. Input the clock to the X1 pin and leave the X2 pin
In the V850ES/JG3-L, an operating clock that is the oscillation frequency multiplied by 4 by the PLL function or an
When PLL function is used: Input clock = 2.5 to 5 MHz (output: 10 to 20 MHz)
Clock-through mode:
PLL Function
Clock output function
External clock signal input
Overview
CLK
Input clock = 2.5 to 10 MHz (output: 2.5 to 10 MHz)
) is selected by using the PCC.CK3 to PCC.CK0 bits.
CHAPTER 6 CLOCK GENERATOR
User’s Manual U18953EJ5V0UD
CLK
) from the CLKOUT pin.
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