UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 811

• Manufacturer Part Number: UPD70F3738GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3738GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

21.5 Exception Trap
V850ES/JG3-L, an illegal opcode exception (ILGOP: Illegal Opcode Trap) is used as an exception trap.
21.5.1 Illegal opcode
to 23) = 0111B to 1111B, and sub-opcode (bit 16) = 0B. When such an instruction is executed, an exception trap
occurs.
An exception trap is an interrupt that is requested when the illegal execution of an instruction takes place. In the
An illegal opcode is defined as an instruction with instruction opcode (bits 10 to 5) = 111111B, sub-opcode (bits 26
Caution Illegal opcodes must not be used because instructions may be newly assigned to these opcodes
(1) Operation
<1> Saves the current PC to DBPC.
<2> Saves the current PSW to DBPSW.
<3> Sets the PSW.NP, PSW.EP, and PSW.ID bits to 1.
<4> Sets the handler address (00000060H) for the exception trap to the PC and transfers control.
If an exception trap occurs, the CPU performs the following processing and transfers control to the handler
routine.
The processing of an exception trap is shown below.
in the future.
×: Arbitrary
15
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CHAPTER 21 INTERRUPT SERVICING/EXCEPTION PROCESSING FUNCTION
×
×
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11
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10
1
1
1
1
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1
5
User’s Manual U18953EJ5V0UD
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4
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0
31
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27 26
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0
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to
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23 22
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× × × × × × 0
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